RFR: 8302908: RISC-V: Support masked vector arithmetic instructions for Vector API [v25]

[Dingli Zhang]

On Mon, 24 Apr 2023 06:12:38 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Add some vector pseudo instructions
>
> src/hotspot/cpu/riscv/riscv_v.ad line 179:
> 
>> 177: %}
>> 178: 
>> 179: instruct vmaskcmp_masked(vRegMask dst, vReg src1, vReg src2, immI cond, vRegMask_V0 vmask, vReg tmp) %{
> 
> I think we can introduce another new operand type (say 'vRegMaskNoV0') which excludes mask register 'v0' for 'dst' here and other places where 'v0' could not be used as the destination register for a masked vector instruction as required by the RVV spec. Then we could eliminate the use of 'tmp' register and 'vmv1r.v' instruction.
> 
> Also, I would like to further rename 'vRegMask_V0 vmask' into 'vRegMask_V0 v0'. The RVV spec says that the mask value used to control execution of a masked vector instruction is always supplied by vector register 'v0' for now.

Fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/12682#discussion_r1174922689