RFR: 8321215: Incorrect x86 instruction encoding for VSIB addressing mode

[Aleksey Shipilev]

On Mon, 4 Dec 2023 19:09:33 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

> For instructions that use VSIB addressing mode (gather/scatter), the assembler incorrectly sets EVEX.X bit when the VSIB vector register is in the range XMM16 - XMM23. The EVEX.X bit should only be set when bit 3 of the register encoding is 1,  i.e. if the register encoding is 8 - 15 or 24 - 31.

Marked as reviewed by shade (Reviewer).

Ah, AMD APM Vol 3, "1.2.8 VEX and XOP Prefixes" is significantly clearer on that part, it just states it adds 1 msb bit to SIB.index, which I think matches the _"high 16"_ in Intel SDM implies.


REX.X: Index field extension (Bit 1). The REX.X bit adds a 1-bit (msb) extension to the 
SIB.index field. See “ModRM and SIB Bytes” on page 17.

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PR Review: https://git.openjdk.org/jdk/pull/16957#pullrequestreview-1763287946
PR Comment: https://git.openjdk.org/jdk/pull/16957#issuecomment-1839375880