RFR: 8321215: Incorrect x86 instruction encoding for VSIB addressing mode

Tue Dec 5 16:15:35 UTC 2023

On Mon, 4 Dec 2023 19:09:33 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

> For instructions that use VSIB addressing mode (gather/scatter), the assembler incorrectly sets EVEX.X bit when the VSIB vector register is in the range XMM16 - XMM23. The EVEX.X bit should only be set when bit 3 of the register encoding is 1,  i.e. if the register encoding is 8 - 15 or 24 - 31.

Looks reasonable. I assume it's not feasible to come up with a regression test, right? I added the 'noreg-hard' label to the bug.

-------------

Marked as reviewed by thartmann (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/16957#pullrequestreview-1765517349