RFR: 8317721: RISC-V: Implement CRC32 intrinsic [v2]

[ArsenyBochkarev]

On Mon, 18 Dec 2023 00:58:33 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Use zero_extend instead of shifts where possible
>>  - Use andn instead of notr + andr where possible
>>  - Replace shNadd with one instruction in most cases
>
> src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp line 1643:
> 
>> 1641:   __ zero_extend(crc, crc, 32);
>> 1642:   __ update_byte_crc32(crc, val, res);
>> 1643:   __ notr(res, crc); // ~crc
> 
> Do you miss the `zero_extend(crc, crc, 32)`?

As far as I can see this is unneeded, actually. I used the `test/hotspot/jtreg/compiler/codegen/CRCTest.java` test as a sanity check (it uses the `emit_updatecrc32` stub) and it's ok.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17046#discussion_r1432711074