RFR: 8301628: RISC-V: c2 fix pipeline class for several instructions

[Feilong Jiang]

On Thu, 2 Feb 2023 01:46:05 GMT, Gui Cao <gcao at openjdk.org> wrote:

> HI,
> 
> The current C2 instructions can use some more accurate ins_pipe, eg.:
> 
> instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
>   match(Set dst (XorI src1 m1));
>   ins_cost(ALU_COST);
>   format %{ "xori  $dst, $src1, -1\t#@regI_not_reg" %}
> 
>   ins_encode %{
>     __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
>   %}
> 
>   ins_pipe(ialu_reg);
> %}
> 
> 
> We can use the more accurate pipe_class `ialu_reg_imm` instead.
> 
> Please take a look and have some reviews. Thanks a lot.
> 
> ## Testing:
> - hotspot and jdk tier1 on unmatched board without new failures

Looks good.

src/hotspot/cpu/riscv/riscv.ad line 7315:

> 7313: 
> 7314: // Float.isInfinite
> 7315: instruct isIniniteF_reg_reg(iRegINoSp dst, fRegF src)

Here is a typo and could you please fix it too?
s/isIniniteF_reg_reg/isInfiniteF_reg_reg

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Marked as reviewed by fjiang (Author).

PR: https://git.openjdk.org/jdk/pull/12379