RFR: 8302453: RISCV: Add support for small width vector operations [v4]

[Dingli Zhang]

On Thu, 16 Feb 2023 03:18:22 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> loadV and vadd.vv have different widths, which are set by vsetvli. Does this have other effects?

@yhzhu20  Thanks for reviewing and good question! 

We refer to the ARM64 implementation[1]. However, in RISC-V, exceptions like overflow/divide by 0 do not cause traps, but instead generate some special default values and set some status bits in the status register.

Considering that the status register may be used in the future, we add a commit to change the full vector operation of other nodes to partial vector operation for vector operations of small width.


[1] https://github.com/openjdk/panama-vector/pull/49

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PR: https://git.openjdk.org/jdk/pull/12553