RFR: 8299525: RISC-V: Add backend support for half float conversion intrinsics [v2]

[Yadong Wang]

On Wed, 4 Jan 2023 13:00:56 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Yadong Wang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   change Zfh to Zfhmin
>
> src/hotspot/cpu/riscv/globals_riscv.hpp line 106:
> 
>> 104:   product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions")             \
>> 105:   product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions")             \
>> 106:   product(bool, UseZfh, false, EXPERIMENTAL, "Use Zfh instructions")             \
> 
> `fcvt.s.h`/`fcvt.h.s`/`fmv_h_x`/`fmv.x.h` also belongs to Zfhmin[1], we can use `UseZfhmin` instead of `UseZfh` here.
> 
> 1. https://github.com/riscv/riscv-isa-manual/blob/cb3b9d1dcdacefbde6602ada7a0050f5c723ddee/src/zfh.tex#L377-L391

Make sense. Fixed.

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PR: https://git.openjdk.org/jdk/pull/11828