RFR: 8300109: RISC-V: Improve code generation for MinI/MaxI nodes [v2]

[Fei Yang]

> As described by the issue, code generation for MinI/MaxI nodes on RISC-V could be improved when one of the source register is the same as the destination register. Also the code could be further simplified when that source register is constant 0 making use of the dedicated zero register of the architecture. This adds new match rules for those cases. 
> 
> Testing:
> - [x] Tier1-3 tested with release build on HiFive Unmatched board.
> - [x] Run non-trivial benchmark workloads (dacapo, specjvm, renaissance, etc) with fastdebug build on HiFive Unmatched board.

Fei Yang has updated the pull request incrementally with one additional commit since the last revision:

  Comment

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Changes:
  - all: https://git.openjdk.org/jdk/pull/11988/files
  - new: https://git.openjdk.org/jdk/pull/11988/files/43cad129..a17a391c

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=11988&range=01
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=11988&range=00-01

  Stats: 42 lines in 1 file changed: 42 ins; 0 del; 0 mod
  Patch: https://git.openjdk.org/jdk/pull/11988.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/11988/head:pull/11988

PR: https://git.openjdk.org/jdk/pull/11988