RFR: 8300109: RISC-V: Improve code generation for MinI/MaxI nodes [v2]

[Aleksey Shipilev]

On Sat, 14 Jan 2023 05:25:12 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> As described by the issue, code generation for MinI/MaxI nodes on RISC-V could be improved when one of the source register is the same as the destination register. Also the code could be further simplified when that source register is constant 0 making use of the dedicated zero register of the architecture. This adds new match rules for those cases. 
>> 
>> Testing:
>> - [x] Run the new jtreg test added by: https://github.com/openjdk/jdk/pull/11570
>> - [x] Tier1-3 tested with release build on HiFive Unmatched board.
>> - [x] Run non-trivial benchmark workloads (dacapo, specjvm, renaissance, etc) with fastdebug build on HiFive Unmatched board.
>
> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Comment

Looks okay. I was wondering if it was possible to have multiple `match(...)`-es per `instruct`, so we could coalesce the symmetric "compare with zero" cases. But it is fine as it is.

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Marked as reviewed by shade (Reviewer).

PR: https://git.openjdk.org/jdk/pull/11988