RFR: 8300247: Harden C1 xchg on AArch64 and PPC

[Fei Yang]

On Wed, 18 Jan 2023 09:00:10 GMT, Erik Österlund <eosterlund at openjdk.org> wrote:

> In the C1 xchg operation, AArch64 and PPC don't deal well with the input register and output register being the same. In some new code, that can happen. This change aims at solving that issue.
> 
> As for AArch64, the xchg implementation in the macro assembler already deals well with the input and output register being the same. So we just need to remove an assert. As for the PPC implementation, @TheRealMDoerr has written a variation that uses a temp operand ensuring that they are not the same register.

Hi, I think we could also relax the same assertion for riscv too.
The bottom 'amoswap.w/d' instruction used in this case does not require that 'dst' and 'obj' are different registers.
Could you please also add this extra small change while are you at it? Thanks.


diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
index aec62aba489..d960d64522c 100644
--- a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
+++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
@@ -1967,7 +1967,8 @@ void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr
           __ encode_heap_oop(t0, obj);
           obj = t0;
         }
-        assert_different_registers(obj, addr.base(), tmp, dst);
+        assert_different_registers(obj, addr.base(), tmp);
+        assert_different_registers(dst, addr.base(), tmp);
         __ la(tmp, addr);
         (_masm->*xchg)(dst, obj, tmp);
         if (is_oop && UseCompressedOops) {

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PR: https://git.openjdk.org/jdk/pull/12065