RFR: 8301153: RISC-V: pipeline class for several instructions is not set correctly

[Feilong Jiang]

Witness that some c2 instructions use the inappropriate ins_pipe, e.g.:


instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{

  match(Set dst (MoveI2F src));

  effect(DEF dst, USE src);

  ins_cost(LOAD_COST);

  format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}

  ins_encode %{
    __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
  %}

  ins_pipe(pipe_class_memory);

%}


We can use the more accurate pipe_class `fp_load_mem_s` instead.

This PR also fixes the side effect of the flags register for two instructions:
We should use/kill a flags register.

Testing:

- [x] Tier1~3 on Unmatched board with release build

-------------

Commit messages:
 - fix pipe_class

Changes: https://git.openjdk.org/jdk/pull/12219/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=12219&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8301153
  Stats: 20 lines in 1 file changed: 1 ins; 0 del; 19 mod
  Patch: https://git.openjdk.org/jdk/pull/12219.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/12219/head:pull/12219

PR: https://git.openjdk.org/jdk/pull/12219