RFR: 8309332: RISC-V: Improve PrintOptoAssembly output of vector nodes

[Yanhong Zhu]

On Fri, 2 Jun 2023 02:08:29 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Hi, Currently in the vector node implementation, some of the instruction formats are part of the rvv assembly instructions, for which the assembly instructions are also incomplete, such as the missing vsetvli assembly instruction(vsetvli is used to set the element width, number, etc), This makes the compiler assembly output by -XX:+PrintOptoAssembly difficult to understand. And if every assembly instruction is reflected, it will be redundant and increase the maintenance work in the future. And referring to other CPUs, such as the ARM64, it is straightforward to use the instruct function name to simplify [1].
> 
> While this won't affect release build, we should fix this for debug build. We can use the -XX:+PrintOptoAssembly parameter to print the compiler assembly output by -XX:+PrintOptoAssembly and view the assembly logic in conjunction with the source code of the specific vector node.
> 
> [1] https://github.com/openjdk/jdk/blob/4460429d7a50b9a7a99058ef4e5ae36fb30b956f/src/hotspot/cpu/aarch64/aarch64_vector.ad#L2842-L2846
> 
> ### Testing:
> qemu with UseRVV:
> 
> - [ ] Tier1 tests (release)
> - [x] test/jdk/jdk/incubator/vector (fastdebug)
> - [x] test/jdk/jdk/incubator/vector/Int256VectorTests.java (fastdebug with -XX:+PrintOptoAssembly)

src/hotspot/cpu/riscv/riscv_v.ad line 1074:

> 1072:   match(Set dst (NegVL src));
> 1073:   ins_cost(VEC_COST);
> 1074:   format %{ "vneg $dst, $src, $src" %}

Hi, for vneg and vfneg, I think `vneg/vfneg $dst, $src` is better.

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PR Review Comment: https://git.openjdk.org/jdk/pull/14279#discussion_r1213856837