RFR: 8309660: C2: failed: XMM register should be 0-15 (UseKNLSetting and ConvF2HF)

[Quan Anh Mai]

On Mon, 12 Jun 2023 09:23:04 GMT, Emanuel Peter <epeter at openjdk.org> wrote:

>> Context: `Float.floatToFloat16` -> `vcvtps2ph`.
>> 
>> **Problem**
>> 
>> vcvtps2ph
>> pre=Assembler::VEX_SIMD_66
>> opc=Assembler::VEX_OPCODE_0F_3A
>> VEX.128.66.0F3A
>> requires F16C
>> 
>> https://www.felixcloutier.com/x86/vcvtps2ph
>> 
>> So this is a non-AVX512 feature, and we should only use the registers `xmm0-15`.
>> 
>> There is also a AVX512 version, but it requires `AVX512VL and AVX512F`.
>> 
>> So on `x64`, we should only use registers `xmm0-15` if we do not have `AVX512VL`, and if we have it, then we can use `xmm0-31`.
>> 
>> **Suggested Solution**
>> As @sviswa7 suggested, we should just use the `vlRegF` instead of `regF`, see discussion in comments.
>> 
>> **Testing**
>> I simulated the patch on intel's `sde`. So now I'm confident that I don't generate code that uses `AVX512VL` registers (XMM16-31).
>> 
>> Running: tier1-6 + stress testing.
>
> @merykitty @sviswa7 @fg1417 Is there a way to stress-test the registers? It seems this bug only triggered because we had a moderately large unrolling factor, and then did not vectorize, leaving lots of instructions with probably a higher register pressure. Would be nice to have some sort of testing where we generate more (all?) of the possible register combinations. What do you think?

@eme64 Yes that was my mistake, that node requires AVX512VL so `vlRegF` and `regF` are the same.

> Is there a way to stress-test the registers?

Can we randomise the allocated register during register allocation?

Thanks.

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PR Comment: https://git.openjdk.org/jdk/pull/14379#issuecomment-1592248071