RFR: 8306966: RISC-V: Support vector cast node for Vector API [v8]

[Feilong Jiang]

On Sat, 6 May 2023 13:15:15 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1823:
>> 
>>> 1821: // High part of dst vector will be filled with zero.
>>> 1822: void C2_MacroAssembler::integer_narrow_v(VectorRegister dst, BasicType dst_bt, int vector_length,
>>> 1823:                                          VectorRegister src, BasicType src_bt, VectorRegister tmp) {
>> 
>> If you allocate different vector registers for 'dst' and 'src' on the callsite, then we should be able to eliminate the 'tmp' register parameter for this function. That is saving the intermediate result in 'dst' instead.
>
> Fixed.

Should we add `assert_differrent_registers` to prevent the same vector register used by other ppl?

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PR Review Comment: https://git.openjdk.org/jdk/pull/13684#discussion_r1186769795