RFR: 8306667: RISC-V: Fix storeImmN0 matching rule by using zr register

[Vladimir Kempik]

On Fri, 21 Apr 2023 10:16:44 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> The `storeImmN0` in the RISC-V backend missed a `CompressedOops::base() == NULL` predication. Under non-zero-based compressed oops mode, the `xheapbase` can be a non-zero value and crashes the VM.
> 
> Reproduced by `<JDK>/bin/java -Xcomp -XX:HeapBaseMinAddress=72030M -version` simply. A hs_err file is attached in the JBS issue.
> 
> x86 uses `r12` as a zero register in `storeImmN0`, but RISC-V has a zero register so we can use it to implement the matching rule.
> 
> Testing in progress.
> 
> Thanks,
> Xiaolin

btw, should this also be backported to 17u-riscv ? after this PR is done

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PR Comment: https://git.openjdk.org/jdk/pull/13577#issuecomment-1517817514