RFR: 8306667: RISC-V: Fix storeImmN0 matching rule by using zr register

Xiaolin Zheng xlinzheng at openjdk.org
Thu May 11 23:16:49 UTC 2023


On Fri, 5 May 2023 07:48:36 GMT, Guoxiong Li <gli at openjdk.org> wrote:

> A potential issue in the comment of [iRegIHeapbase](https://github.com/openjdk/jdk/blob/302bc2fd7fdfc02314e22ecc34ba2c78ef5ca9a1/src/hotspot/cpu/riscv/riscv.ad#L3544):
> 
> ```
> // heap base register -- used for encoding immN0
> operand iRegIHeapbase()
> ```
> 
> And unfortunately, `aarch64` has the same issue in [iRegIHeapbase](https://github.com/openjdk/jdk/blob/302bc2fd7fdfc02314e22ecc34ba2c78ef5ca9a1/src/hotspot/cpu/aarch64/aarch64.ad#L5241) since [JDK-8242449](https://bugs.openjdk.org/browse/JDK-8242449).
> 
> They can be fixed together in a follow-up patch. Or only fix the `riscv64` part in this patch and fix the `aarch64` part in another patch.

Indeed, `iRegIHeapbase` gets used nowhere in both backends and thanks for the catching. I can file one patch to clean them up after this.

Though, I think the AArch64 backend does not have this issue because it has the [`CompressedOops::base() == NULL && CompressedKlassPointers::base() == NULL`](https://hg.openjdk.org/jdk/jdk/rev/aedc9bf21743#l1.24) guard before JDK-8242449 - if I understand your comments correctly?

P.S. Sorry for the delay in this fix - I have tested hotspot tier1~4 on QEMU but still not yet on an unmatched board since mine has other jobs to test. Will carry this fix on soon.

-------------

PR Comment: https://git.openjdk.org/jdk/pull/13577#issuecomment-1536003434


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