Integrated: 8306667: RISC-V: Fix storeImmN0 matching rule by using zr register

[Xiaolin Zheng]

On Fri, 21 Apr 2023 10:16:44 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> The `storeImmN0` in the RISC-V backend missed a `CompressedOops::base() == NULL` predication. Under non-zero-based compressed oops mode, the `xheapbase` can be a non-zero value and crashes the VM.
> 
> Reproduced by `<JDK>/bin/java -Xcomp -XX:HeapBaseMinAddress=72030M -version` simply. A hs_err file is attached in the JBS issue.
> 
> x86 uses `r12` as a zero register in `storeImmN0`, but RISC-V has a zero register so we can use it to implement the matching rule.
> 
> Testing in progress.
> 
> Thanks,
> Xiaolin

This pull request has now been integrated.

Changeset: e32de7ef
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/e32de7efd6f3173a0bba5829e8de3edd01cfdbab
Stats:     3 lines in 1 file changed: 0 ins; 0 del; 3 mod

8306667: RISC-V: Fix storeImmN0 matching rule by using zr register

Reviewed-by: shade, gli, fyang

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PR: https://git.openjdk.org/jdk/pull/13577