RFR: 8307609: RISC-V: Added support for Extract, Compress, Expand and other nodes for Vector API [v8]

[Dingli Zhang]

On Wed, 17 May 2023 12:52:27 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Shouldn't this be: `__ vcpop_m($dst$$Register, as_VectorRegister($tmp$$reg), Assembler::v0_t);`? And do we missed `VectorMaskLastTrue`?

Based on our research, we have found that RISC-V does not require the addition of the `vmask_firsttrue_masked` node (currently only present in ARM64). This is because current we already have the application vector length or AVL setting in RISC-V. 
Therefore, the `VectorMaskFirstTrue` node on RISC-V does not need a partial operation to substitute vector length for vector register size, as in ARM64:
https://github.com/openjdk/jdk/blob/3c9ec26370dfae5d1230b6b69ae26122fe42e51d/src/hotspot/cpu/aarch64/aarch64_vector.ad#L290-L294
We will remove `vmask_firsttrue_masked` next.

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PR Review Comment: https://git.openjdk.org/jdk/pull/13862#discussion_r1197487563