RFR: 8308656: RISC-V: vstring_compare doesnt manifest usage of all vector registers [v2]

[Vladimir Kempik]

On Wed, 24 May 2023 04:07:10 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Vladimir Kempik has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Revert part of the fix
>
> src/hotspot/cpu/riscv/riscv_v.ad line 2227:
> 
>> 2225:                           iRegI_R10 result, vReg_V1 v1, vReg_V2 v2, vReg_V3 v3, vReg_V4 v4,
>> 2226:                           vReg_V5 v5, vReg_V6 v6, vReg_V7 v7,
>> 2227:                           vRegMask_V0 v0, iRegP_R28 tmp1, iRegL_R29 tmp2)
> 
> Hi,
> When StrCompNode is `StrIntrinsicNode::UU` or `StrIntrinsicNode::LL`,  if-branch (element_compare) will be executed in `C2_MacroAssembler::string_compare_v`, and `lmul` is set to 2, so v6 and v7 are not used in `string_compareL` and `string_compareU`, here is the code:
> C2_MacroAssembler::string_compare_v
> 
>   if (str1_isL == str2_isL) { // LL or UU
>     element_compare(str1, str2, zr, cnt2, tmp1, tmp2, v2, v4, v1, encLL, DIFFERENCE);
>     j(DONE);
>   } else { // LU or UL
>     Register strL = encLU ? str1 : str2;
>     Register strU = encLU ? str2 : str1;
> 
> C2_MacroAssembler::element_compare
> 
>  bind(loop);
>   vsetvli(tmp1, cnt, sew, Assembler::m2);
>   vlex_v(vr1, a1, sew);
>   vlex_v(vr2, a2, sew);
> 
> So we don't need to do this for the LL and UU case.

Right, thank you

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/14102#discussion_r1204399890