RFR: 8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0

[Dingli Zhang]

We have some macro assembler functions that use v0 hardcoded as a temporary
register currently.

However, the mask value used to control execution of a masked vector
instruction is always supplied by vector register v0 in RVV1.0[1]. So if v0 is
not used as a mask register in subsequent instructions, it is better to
replace it with other vector registers to improve code execution efficiency.

In addition, this pr also adds several missing spaces in the format of the
instructions, and fixes several pipeline classes.

[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc

## Testing:
QEMU w/ UseRVV:
- [x] Tier1 tests (release)
- [ ] Tier2 tests (release)
- [ ] Tier3 tests (release)
- [x] test/jdk/jdk/incubator/vector (fastdebug)

-------------

Commit messages:
 - 8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0

Changes: https://git.openjdk.org/jdk/pull/14166/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=14166&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8308915
  Stats: 124 lines in 3 files changed: 61 ins; 0 del; 63 mod
  Patch: https://git.openjdk.org/jdk/pull/14166.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/14166/head:pull/14166

PR: https://git.openjdk.org/jdk/pull/14166