RFR: 8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0

[Fei Yang]

On Fri, 26 May 2023 02:36:42 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> We have some macro assembler functions that use v0 hardcoded as a temporary
> register currently.
> 
> However, the mask value used to control execution of a masked vector 
> instruction is always supplied by vector register v0 in RVV1.0[1]. If v0 is 
> alive holding a mask value the the same time,  this will cause spilling of 
> this vector register. So it is better to replace v0 with other vector registers to 
> improve code execution efficiency.
> 
> In addition, this pr also adds several missing spaces in the format of the
> instructions, and fixes several pipeline classes.
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
> 
> ## Testing:
> QEMU w/ UseRVV:
> - [x] Tier1 tests (release)
> - [ ] Tier2 tests (release)
> - [ ] Tier3 tests (release)
> - [x] test/jdk/jdk/incubator/vector (fastdebug)

Looks fine.

Marked as reviewed by fyang (Reviewer).

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PR Review: https://git.openjdk.org/jdk/pull/14166#pullrequestreview-1445821108
PR Review: https://git.openjdk.org/jdk/pull/14166#pullrequestreview-1445821588