RFR: 8308915: RISC-V: Improve temporary vector register usage avoiding the use of v0 [v2]

[Dingli Zhang]

> We have some macro assembler functions that use v0 hardcoded as a temporary
> register currently.
> 
> However, the mask value used to control execution of a masked vector 
> instruction is always supplied by vector register v0 in RVV1.0[1]. If v0 is 
> alive holding a mask value the the same time,  this will cause spilling of 
> this vector register. So it is better to replace v0 with other vector registers to 
> improve code execution efficiency.
> 
> In addition, this pr also adds several missing spaces in the format of the
> instructions, and fixes several pipeline classes.
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
> 
> ## Testing:
> QEMU w/ UseRVV:
> - [x] Tier1 tests (release)
> - [x] Tier2 tests (release)
> - [x] Tier3 tests (release)
> - [x] test/jdk/jdk/incubator/vector (fastdebug)

Dingli Zhang has updated the pull request incrementally with one additional commit since the last revision:

  Fix comment

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/14166/files
  - new: https://git.openjdk.org/jdk/pull/14166/files/05446b0a..9fea08dc

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=14166&range=01
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=14166&range=00-01

  Stats: 1 line in 1 file changed: 0 ins; 0 del; 1 mod
  Patch: https://git.openjdk.org/jdk/pull/14166.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/14166/head:pull/14166

PR: https://git.openjdk.org/jdk/pull/14166