RFR: 8303417: RISC-V: Merge vector instructs with similar match rules

[Fei Yang]

On Tue, 30 May 2023 12:11:43 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> Merge vector instructs with similar match rules in riscv_v.ad.
> 
> Tier 1~3 passed on QEMU with RVV supported.

Thanks for the cleanup. One minor comment.

src/hotspot/cpu/riscv/riscv_v.ad line 245:

> 243:   ins_cost(VEC_COST);
> 244:   effect(TEMP tmp);
> 245:   format %{ "vrsub.vi $tmp, 0, $src\t#@vabs\n\t"

Suggestion: `format %{ "vrsub.vi $tmp, $src, 0\t#@vabs\n\t"`

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Changes requested by fyang (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/14214#pullrequestreview-1452262058
PR Review Comment: https://git.openjdk.org/jdk/pull/14214#discussion_r1211125319