RFR: 8319184: RISC-V: improve MD5 intrinsic

[Antonios Printezis]

On Thu, 2 Nov 2023 13:16:30 GMT, Antonios Printezis <tonyp at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4133:
>> 
>>> 4131:     Register state1    =  x6; // t1
>>> 4132:     Register state2    =  x7; // t2
>>> 4133:     Register state3    = x20; // s4
>> 
>> I don't think it's safe to use x5 (t0) / x6 (t1) to keep some long-lived values like `state0` / `state1`. Those two are reserved scratch registers which could be explictly / implicitly clobberred by various assembler functions like [1]. 
>> 
>> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp#L760-L763
>
> Yeah, I tried to make sure that I pass any temp registers to such functions explicitly, but you're right, it can be error prone. Should I just use s4 -> s7 for the 4 state registers?

Hmmm... Maybe I don't need to declare / use `tmp3` and just use `t0` in `add_u32`? Sounds reasonable?

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PR Review Comment: https://git.openjdk.org/jdk/pull/16453#discussion_r1380087542