RFR: 8319184: RISC-V: improve MD5 intrinsic [v2]

[Antonios Printezis]

On Mon, 6 Nov 2023 04:51:42 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Antonios Printezis has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   changes based on code review
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3984:
> 
>> 3982:               Register a, Register b, Register c, Register d,
>> 3983:               int k, int s, int t,
>> 3984:               Register rtmp1, Register rtmp2) {
> 
> Now that we have scratch register `t0` available for use in functions md5_FF/GG/HH/II, we could further remove use of `rtmp2`. Then we might want to let `rtmp1` = `t2` while use `x10`-`x11` for `state0`-`state1`. This will help save use of one callee-saved register. Please consider.

It was actually a conscious decision to use different registers (`a0`/`a1`) for the intermediate results in `md5_FF/GG/HH/II` than the registers (`t0` / `t1`) used in `m5_FF_GG_HH_II_epilogue`. Fewer register dependencies between instructions can maybe help some cpus. Also, `rtmp1` / `rtmp2` being `a0` / `a1` allows the use of compressed instructions in a couple of places (if we care about compressed instructions that is!).

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PR Review Comment: https://git.openjdk.org/jdk/pull/16453#discussion_r1383558782