RFR: 8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock [v2]

[Gui Cao]

> This is inspired by https://bugs.openjdk.org/browse/JDK-8316880.
> MacroAssembler::lightweight_lock/unlock is non-trivial on linux-riscv64 platform. Passing t0(aka x5) as temporary register to these two assember functions can also be error prone. As a reserved scratch register, t0 is implicitly clobberred by various assembler functions. This fixes the issue by finding and passing a different register, which is similar with https://bugs.openjdk.org/browse/JDK-8316880.
> 
> ### Testing:
> - [x]  Run tier1-3 tests with qemu 8.1.50 (default locking mode) (release)
> - [x]  Run non-trivial benchmark workloads (specjbb2005, dacapo, renaissance) with -XX:LockingMode=2 (fastdebug & release)
> - [x] hotspot:tier4 on hifive unmatched (release)

Gui Cao has updated the pull request incrementally with one additional commit since the last revision:

  Update some assertions for calls to MacroAssembler::lightweight_lock/unlock

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/16703/files
  - new: https://git.openjdk.org/jdk/pull/16703/files/eccb82c9..ca4402f8

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=16703&range=01
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=16703&range=00-01

  Stats: 4 lines in 2 files changed: 0 ins; 0 del; 4 mod
  Patch: https://git.openjdk.org/jdk/pull/16703.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/16703/head:pull/16703

PR: https://git.openjdk.org/jdk/pull/16703