RFR: 8320280: RISC-V: Avoid passing t0 as temp register to MacroAssembler::lightweight_lock/unlock [v2]

[Robbin Ehn]

On Mon, 20 Nov 2023 10:23:28 GMT, Gui Cao <gcao at openjdk.org> wrote:

> > Hi, thanks!
> > Sorry with callee I meant all methods that have cmpxchg in them, such macroAssembler_riscv.cpp: MacroAssembler::lightweight_(un)lock Where this assert is also assert_different_registers(obj, hdr, tmp1, tmp2); So there are a couple of more, sorry.
> > There also a special cmpxchg_obj_header which still uses t0. You want to fix that in this same PR?
> 
> Hi @robehn, I am not sure if understand it correctly. Do you want me to revert my last comment and add `t0` in the list of `assert_different_registers` in MacroAssembler::lightweight_(un)lock? I think it might be better to handle the special case for cmpxchg_obj_header in another PR, is that OK for you?

If you don't mind, just add t0 in those asserts. The other asserts are also useful for the reader to what is expected without needing to trace down the entire call chain, so no need to revert anything.

Yes, sure, sHould I or you create jira issue ?

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PR Comment: https://git.openjdk.org/jdk/pull/16703#issuecomment-1818785877