RFR: 8317971: RISC-V: implement copySignF/D and signumF/D intrinsics [v2]

[Ilya Gavrilin]

On Tue, 17 Oct 2023 09:09:52 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Ilya Gavrilin has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fix some registers usages and typos
>
> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 1682:
> 
>> 1680:   // use floating-point 1.0 with a sign of input
>> 1681:   is_double ? fsgnj_d(dst, one, src)
>> 1682:             : fsgnj_s(dst, one, src);
> 
> What if the `src` argument contains zero? Math.signum(float/double) is supposed to return zero if the argument is zero [1].
> 
> [1] https://github.com/openjdk/jdk/blob/master/src/java.base/share/classes/java/lang/Math.java#L2602

According to IEEE754, we can get positive or negative zero in the `src` register (also positive zero can be named as zero) , and these cases included to mask for the tmp1 (L1671-1676) and `src` value returned.

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PR Review Comment: https://git.openjdk.org/jdk/pull/16186#discussion_r1361840030