RFR: 8328998: Encoding support for Intel APX extended general-purpose registers

[Vladimir Kozlov]

On Mon, 25 Mar 2024 19:01:17 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

> Add instruction encoding support for Intel APX extended general-purpose registers:
> 
> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
> 
> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.

I have few comments.

src/hotspot/cpu/x86/assembler_x86.cpp line 669:

> 667:       // [base + disp]
> 668:       assert(((base_enc & 0x7) != 4), "illegal addressing mode");
> 669:       if (disp == 0 && no_relocation &&  ((base_enc & 0x7) != 5)) {

We loost information with this change. Can it be done as `is_r13_encoding(base_enc)` and `is_r12_enxoding(base_enc)`?

src/hotspot/cpu/x86/assembler_x86.hpp line 790:

> 788:   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
> 789:                              VexSimdPrefix pre, VexOpcode opc,
> 790:                              InstructionAttr *attributes, bool src_is_gpr = false);

I saw a lot of usage of this method with `src_is_gpr` is `true`. What is actual most common case?

src/hotspot/cpu/x86/assembler_x86.hpp line 796:

> 794: 
> 795:   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
> 796:                              VexOpcode opc, InstructionAttr *attributes, bool src_is_gpr = false);

Same question as for `vex_prefix_and_encode`

src/hotspot/cpu/x86/globals_x86.hpp line 236:

> 234:              "mitigations for the Intel JCC erratum")                       \
> 235:                                                                             \
> 236:   product(bool, UseAPX, false, EXPERIMENTAL,                                              \

Spacing to ``

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PR Review: https://git.openjdk.org/jdk/pull/18476#pullrequestreview-2001791276
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1566209314
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1566215878
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1566216494
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1566217674