RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v3]

[Sandhya Viswanathan]

On Fri, 19 Apr 2024 21:38:53 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

>> Add instruction encoding support for Intel APX extended general-purpose registers:
>> 
>> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>> 
>> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.
>
> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
> 
>   bug fix in ::prefix_rex2

src/hotspot/cpu/x86/assembler_x86.cpp line 12969:

> 12967: void Assembler::prefix_rex2(Address adr, Register reg, bool byteinst, bool is_map1) {
> 12968:   int bits = is_map1 ? REX2BIT_M0 : 0;
> 12969:   bits |= get_base_prefix_bits(adr.base()->encoding());

This also needs fix to:
bits |= get_base_prefix_bits(adr.base());

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1572995583