RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v5]

[Sandhya Viswanathan]

On Fri, 26 Apr 2024 20:44:03 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

>> Add instruction encoding support for Intel APX extended general-purpose registers:
>> 
>> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>> 
>> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.
>
> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
> 
>   from review comments: simplification, fix comments and white space

Should is_src_gpr be set to true for the additional following instructions as well:
void Assembler::pextrd(Register dst, XMMRegister src, int imm8)
void Assembler::pextrq(Register dst, XMMRegister src, int imm8)
void Assembler::pextrb(Register dst, XMMRegister src, int imm8)  
void Assembler::extractps(Register dst, XMMRegister src, uint8_t imm8)  
void Assembler::pextl(Register dst, Register src1, Address src2)  
void Assembler::pdepl(Register dst, Register src1, Address src2)  
void Assembler::pextq(Register dst, Register src1, Address src2)  
void Assembler::pdepq(Register dst, Register src1, Address src2)  
void Assembler::movdq(Register dst, XMMRegister src)

Also the following instruction is not handled for egprs:
void Assembler::popq(Register dst)

It looks to me that the source and dest are reversed in the following instruction in call to simd_prefix_and_encode, perhaps that should be a separate PR:
// Do we have this wrong src and dst reversed in simd_prefix_and_encode?
void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
  assert(VM_Version::supports_sse2(), "");
  InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
  int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
  emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
}
Once that PR is fixed, is_src_gpr should be set to true for this one as well.

-------------

PR Comment: https://git.openjdk.org/jdk/pull/18476#issuecomment-2080217467
PR Comment: https://git.openjdk.org/jdk/pull/18476#issuecomment-2080217893
PR Comment: https://git.openjdk.org/jdk/pull/18476#issuecomment-2080219230