RFR: 8321008: RISC-V: C2 MulAddVS2VI

[Fei Yang]

On Tue, 23 Apr 2024 15:02:10 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review the patch?
> 
> The motivation is to implement `MulAddVS2VI`.
> But to enable `MulAddVS2VI`, `MulAddS2I` is prerequisite, although `MulAddS2I` does not bring extra benefit on riscv as we don't have an specific instruction of muladd on riscv.
> So, this patch implement both `MulAddVS2VI` and `MulAddS2I`. 
> 
> Thanks

src/hotspot/cpu/riscv/riscv_v.ad line 898:

> 896: 
> 897:     __ vmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), as_VectorRegister($tmp2$$reg));
> 898:     __ vmacc_vv(as_VectorRegister($dst$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp3$$reg));

Hmm ... This doesn't look like a simple/straightforward sequence, isn't it? It's hard to tell whether we will benifit from this change without JMH testing on real RVV hardwares especially when VLEN is not large (No big difference in respect of number of instructions executed when VLEN=128-bits).

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PR Review Comment: https://git.openjdk.org/jdk/pull/18919#discussion_r1583085528