RFR: 8321008: RISC-V: C2 MulAddVS2VI

[Fei Yang]

On Tue, 23 Apr 2024 15:02:10 GMT, Hamlin Li <mli at openjdk.org> wrote:

> Hi,
> Can you help to review the patch?
> 
> The motivation is to implement `MulAddVS2VI`.
> But to enable `MulAddVS2VI`, `MulAddS2I` is prerequisite, although `MulAddS2I` does not bring extra benefit on riscv as we don't have an specific instruction of muladd on riscv.
> So, this patch implement both `MulAddVS2VI` and `MulAddS2I`. 
> 
> Thanks

src/hotspot/cpu/riscv/riscv.ad line 6614:

> 6612:   ins_encode %{
> 6613:     __ mul(t0, as_Register($src1$$reg), as_Register($src2$$reg));
> 6614:     __ mul(t1, as_Register($src3$$reg), as_Register($src4$$reg));

Note that it's risky to use `t1` here as it's the flags register for C2 on riscv. So you might want to reserve another temporary register to replace it.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18919#discussion_r1583112081