RFR: 8321008: RISC-V: C2 MulAddVS2VI [v2]

[Hamlin Li]

On Mon, 29 Apr 2024 13:55:21 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> You're right.
>> 
>> I'm not quite familiar with this part. Just a question about the flag register (t1) in riscv, do we already use t1 as flag register in any code? I've worked on something related to it, but seems it's not performant (https://bugs.openjdk.org/browse/JDK-8320989)
>
> Yes and you will find some usages if you grep "Set cr" in file riscv.ad: 
> 
>   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
>   match(Set cr (FastLock object box));
>   match(Set cr (FastUnlock object box));
>   match(Set cr (FastLock object box));
>   match(Set cr (FastUnlock object box));
> 
> 
> These C2 nodes are expecting a result in the flag register (aka `rFlagsReg cr`):
> 
>  3814 // Flags register, used as output of compare logic
>  3815 operand rFlagsReg()
>  3816 %{
>  3817   constraint(ALLOC_IN_RC(reg_flags));
>  3818   match(RegFlags);
>  3819
>  3820   op_cost(0);
>  3821   format %{ "RFLAGS" %}
>  3822   interface(REG_INTER);
>  3823 %}
> 
> 
> And the result will be further used by compare flags and branch instructions like:
> 
> match(If cmp cr);

Thanks, I've updated it to use a passed in tmp reg.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18919#discussion_r1583170683