RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v5]

[Steve Dohrmann]

On Fri, 26 Apr 2024 23:07:44 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

>> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   from review comments: simplification, fix comments and white space
>
> It looks to me that the source and dest are reversed in the following instruction in call to simd_prefix_and_encode, perhaps that should be a separate PR:
> // Do we have this wrong src and dst reversed in simd_prefix_and_encode?
> void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
>   assert(VM_Version::supports_sse2(), "");
>   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
>   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
>   emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
> }
> Once that PR is fixed, is_src_gpr should be set to true for this one as well.

@sviswa7 wrote
> Also the following instruction is not handled for egprs: void Assembler::popq(Register dst)

Thank you.  Updated popq(Register) for egpr support.

-------------

PR Comment: https://git.openjdk.org/jdk/pull/18476#issuecomment-2083747132