RFR: 8329035: New Data Destination instructions support

[Jatin Bhateja]

On Fri, 23 Aug 2024 22:44:09 GMT, Steve Dohrmann <sdohrmann at openjdk.org> wrote:

> Adds assembler support for APX New Data Destination (NDD) and No Flags (NF) features.  
> 
> The NDD feature is supported by new functions that take an additional destination-only register operand.  If the instruction also supports NF, a no_flags boolean parameter is present. To use these instructions with NF behavior, but without NDD semantics, the same register can be supplied for both the new destination and the (first) source operand.
> 
> Some instructions support NF but not NDD.  These instructions have a new function that just adds a boolean no_flags parameter.  Existing functions were not overloaded with a boolean here because of  signature collisions (bool / int) with functions that take immediate operands.
> 
> All of the new functions have a letter "e" prefix, to avoid signature collisions and to indicate they will be evex encoded.

src/hotspot/cpu/x86/assembler_x86.cpp line 1579:

> 1577: 
> 1578: void Assembler::eaddl(Register dst, Register src1, Register src2, bool no_flags) {
> 1579:   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);

Should we not auto demote these instruction to use legacy MAP0 encoding, if dst and src1 / src2 are same and does not belong to EGPR set?
We do REX to VEX promotion and EVEX to VEX demotions at assembler level if the required criteria is met.

src/hotspot/cpu/x86/assembler_x86.cpp line 2647:

> 2645:   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
> 2646:   attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
> 2647:   vex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);

Suggestion:

  eevex_prefix_ndd(src, dst->encoding(), 0, VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);

src/hotspot/cpu/x86/assembler_x86.hpp line 794:

> 792:                        bool eevex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool no_flags = false);
> 793: 
> 794:   void vex_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false) {

Suggestion:

  void eevx_prefix_ndd(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false) {


NDD is only supported with 4 byte extended evex encoding.

src/hotspot/cpu/x86/assembler_x86.hpp line 798:

> 796:   }
> 797: 
> 798:   void vex_prefix_nf(Address adr, int ndd_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes, bool no_flags = false) {

Same as above.

src/hotspot/cpu/x86/assembler_x86.hpp line 809:

> 807:                              InstructionAttr *attributes, bool src_is_gpr = false, bool nds_is_ndd = false, bool force_evex = false, bool no_flags = false);
> 808: 
> 809:   int  vex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,

Suggestion:

  int  vex_prefix_and_encode_ndd(int ndd_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,

src/hotspot/cpu/x86/assembler_x86.hpp line 811:

> 809:   int  vex_prefix_and_encode_ndd(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
> 810:                              InstructionAttr *attributes, bool no_flags = false) {
> 811:     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true , /* force_evex */ true, no_flags);

Suggestion:

    return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true , /* force_evex */ true, no_flags);

Suggestion:

    return vex_prefix_and_encode(ndd_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ true , /* force_evex */ true, no_flags);

src/hotspot/cpu/x86/assembler_x86.hpp line 814:

> 812:   }
> 813: 
> 814:   int  vex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,

Suggestion:

  int  vex_prefix_and_encode_nf(int ndd_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,

src/hotspot/cpu/x86/assembler_x86.hpp line 816:

> 814:   int  vex_prefix_and_encode_nf(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc,
> 815:                              InstructionAttr *attributes, bool no_flags = false) {
> 816:     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, /* force_evex */ true, no_flags);

Suggestion:

    return vex_prefix_and_encode(ndd_enc, nds_enc, src_enc, pre, opc, attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, /* force_evex */ true, no_flags);

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734889129
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1735083052
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734877069
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734877452
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734908102
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734908555
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734909059
PR Review Comment: https://git.openjdk.org/jdk/pull/20698#discussion_r1734909377