RFR: 8317721: RISC-V: Implement CRC32 intrinsic [v4]

[ArsenyBochkarev]

On Wed, 10 Jan 2024 06:06:37 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with four additional commits since the last revision:
>> 
>>  - Fix unroll size
>>  - Rename constants
>>  - Partially unroll loop
>>  - Optimize loop counter in L_by16_loop
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4655:
> 
>> 4653:     const Register table3 = c_rarg6;
>> 4654: 
>> 4655:     const Register tmp1 = t0;
> 
> As previously discussed elsewhere, it is error-prone to create aliases for scratch registers like `t0` and pass as parameters to other assember functions. It will be safer if we use `t0` directly in `kernel_crc32` and remove the `tmp` formal parameter of `kernel_crc32`. (Also safer to use `c_rarg7` instead of `t1` for `tmp2`)

Fixed: now the `c_rarg7` used as `tmp1`, `t2` as `tmp2`, etc.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17046#discussion_r1494877119