RFR: 8327041: Incorrect lane size references in avx512 instructions.

[Jatin Bhateja]

- As per AVX-512 instruction format, a memory operand instruction can use compressed disp8*N encoding.
- For instructions which reads/writes entire vector from/to memory, scaling factor (N) computation only takes into account vector length and is not dependent on vector lane sizes[1].
- Patch fixes incorrect lane size references from various x86 assembler routines, this is not a functionality bug, but correcting the lane size will make the code compliant with AVX-512 instruction format specification.

[1] Intel SDM, Volume 2, Section 2.7.5 Table 2-35
    https://cdrdv2.intel.com/v1/dl/getContent/671200

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Commit messages:
 - 8327041: Incorrect lane size references in avx512 instructions.

Changes: https://git.openjdk.org/jdk/pull/18059/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=18059&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8327041
  Stats: 81 lines in 1 file changed: 0 ins; 0 del; 81 mod
  Patch: https://git.openjdk.org/jdk/pull/18059.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/18059/head:pull/18059

PR: https://git.openjdk.org/jdk/pull/18059