RFR: 8317720: RISC-V: Implement Adler32 intrinsic [v18]

[ArsenyBochkarev]

On Wed, 17 Jul 2024 04:26:06 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Eliminate L_simple_by1_loop
>>  - Use small lmul to be consistent in naming style
>>  - Use temp3 instead of t2 as a scratch register
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 5149:
> 
>> 5147:     Register temp1 = c_rarg5;
>> 5148:     Register temp2 = c_rarg6;
>> 5149:     Register temp3 = x28; // t3
> 
> Nit: Let's change the register assignment a bit so that it will be cleaner.
> 
>     Register nmax  = c_rarg4;
>     Register base  = c_rarg5;
>     Register count = c_rarg6;
>     Register temp0 = x28; // t3
>     Register temp1 = x29; // t4
>     Register temp2 = x30; // t5
>     Register temp3 = x31; // t6

Done! BTW, JFYI: I decided to move a bit back and generate all tables explicitly regardless of `MaxVectorSize`, IMHO it is much easier to read

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PR Review Comment: https://git.openjdk.org/jdk/pull/18382#discussion_r1681081151