RFR: 8331117: [PPC64] secondary_super_cache does not scale well [v6]

[Martin Doerr]

On Fri, 14 Jun 2024 15:35:43 GMT, Amit Kumar <amitkumar at openjdk.org> wrote:

>> Martin Doerr has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Minor improvements according to review suggestions.
>
> src/hotspot/cpu/ppc/macroAssembler_ppc.cpp line 2160:
> 
>> 2158:          r_array_length == R5_ARG3                                 && \
>> 2159:          (r_array_index == R6_ARG4      || r_array_index == noreg) && \
>> 2160:          (r_sub_klass   == R7_ARG5      || r_sub_klass   == noreg) && \
> 
> Maybe we can set `r_super_klass = R5` and `r_sub_klass =R7` to keep consistency in `c1_Runtime1_ppc.cpp`:
> 
> 
>     case slow_subtype_check_id:
>       { // Support for uint StubRoutine::partial_subtype_check( Klass sub, Klass super );
>         const Register sub_klass = R5,
>                        super_klass = R4,
>                        temp1_reg = R6,
>                        temp2_reg = R0;
>         __ check_klass_subtype_slow_path(sub_klass, super_klass, temp1_reg, temp2_reg); // returns with CR0.eq if successful
>         __ crandc(CCR0, Assembler::equal, CCR0, Assembler::equal); // failed: CR0.ne
>         __ blr();
>       }
>       break;
> 
> 
> I can see this being done for `aarch64`, `x86` and `risc-v` as well.

Ok, using the same registers for sub_klass and super_klass as C1 should do no harm. See latest commit.

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PR Review Comment: https://git.openjdk.org/jdk/pull/19368#discussion_r1640355111