RFR: 8327041: Incorrect lane size references in avx512 instructions.

[Sandhya Viswanathan]

On Thu, 29 Feb 2024 11:09:09 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> - As per AVX-512 instruction format, a memory operand instruction can use compressed disp8*N encoding.
> - For instructions which reads/writes entire vector from/to memory, scaling factor (N) computation only takes into account vector length and is not dependent on vector lane sizes[1].
> - Patch fixes incorrect lane size references from various x86 assembler routines, this is not a functionality bug, but correcting the lane size will make the code compliant with AVX-512 instruction format specification.
> 
> [1] Intel SDM, Volume 2, Section 2.7.5 Table 2-35
>     https://cdrdv2.intel.com/v1/dl/getContent/671200

Looks good to me.

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Marked as reviewed by sviswanathan (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/18059#pullrequestreview-1926014748