RFR: 8320725: C2: Add "is_associative" flag for floating-point add-reduction [v2]

[Jatin Bhateja]

On Wed, 13 Mar 2024 17:17:36 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

> 
> **> Why does you patch not do anything for x86? I guess x86 AD-files have no float/double reduction for the associative case, only the non-associative (strict order). But I think it would be easy to implement, just take the code used for int/long etc reductions.** Well, what I meant was that the changes in this patch (specifically the mid-end part) do not break/change anything in x86 (or any other platform). Yes, the current *.ad files might have rules only for the strict order case and more rules can be added for non-associative case if that benefits x86 (same for other platforms). So for aarch64, we have different instruction(s) for floating-point strict order/non-strict order and we know which ones are beneficial to be generated on which aarch64 machines. I could have tried but I am not very well versed with x86 ISA and would request anyone from Intel or someone who has the expertise with x86 ISA to make x86 related changes please (if required). Maybe Jatin/Sandhya can help here
 ? I am unable to tag them for some reason.
> 

I agree, as per following Vector API documentation, backends are free to deviate from JVM specification (15.18.2) which enforces non-associativity on FP operation.
https://docs.oracle.com/en/java/javase/21/docs/api/jdk.incubator.vector/jdk/incubator/vector/VectorOperators.html#fp_assoc:~:text=Certain%20associative%20operations,this%20machine%20code. 
You may create a follow-up RFE for x86 side of optimization and assign it to me.

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PR Comment: https://git.openjdk.org/jdk/pull/18034#issuecomment-2003174869