RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v14]

[Jatin Bhateja]

On Fri, 3 May 2024 19:14:07 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

>> Add instruction encoding support for Intel APX extended general-purpose registers:
>> 
>> Intel Advanced Performance Extensions (APX) doubles the number of general-purpose registers, from 16 to 32. For more information about APX, see https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html.
>> 
>> By specification, instruction encoding remains unchanged for instructions using only the lower 16 GPRs. For cases where one or more instruction operands reference extended GPRs (Egprs), encoding targets either REX2, an extension of REX encoding, or an extended version of EVEX encoding. These new encoding schemes extend or modify existing instruction prefixes only when Egprs are used.
>
> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
> 
>   revert unneeded legacy flag change for kmovwl(K,K) and kmovql(K,K)

src/hotspot/cpu/x86/assembler_x86.cpp line 11754:

> 11752: 
> 11753: // This is a 4 byte encoding
> 11754: void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_b, bool evex_v,

Suggestion:

void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool eevex_b, bool evex_v,

src/hotspot/cpu/x86/assembler_x86.cpp line 11766:

> 11764:   // P0: byte 2, initialized to RXBR`00mm
> 11765:   // instead of not'd
> 11766:   int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);

Comment at [L#11765 
](https://github.com/openjdk/jdk/pull/18476/files#diff-e3576e9c22db89236cdb906f032ff00748ff6d1c21b05277d991d80af75daf3aL11686)
`// P0: byte 2, initialized to RXBR'00mm  => // P0: byte 2, initialized to RXBR'0mmm`

src/hotspot/cpu/x86/assembler_x86.cpp line 11768:

> 11766:   int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
> 11767:   byte2 = (~byte2) & 0xF0;
> 11768:   byte2 |= evex_b ? EEVEX_B : 0;

Suggestion:

  byte2 |= eevex_b ? EEVEX_B : 0;


This corresponds to B4 bit which is specific to EEVEX encoding.

src/hotspot/cpu/x86/assembler_x86.cpp line 11846:

> 11844:     }
> 11845:     bool eevex_x = adr.index_needs_rex2();
> 11846:     bool evex_b = adr.base_needs_rex2();

Suggestion:

    bool eevex_b = adr.base_needs_rex2();

src/hotspot/cpu/x86/assembler_x86.cpp line 11848:

> 11846:     bool evex_b = adr.base_needs_rex2();
> 11847:     attributes->set_is_evex_instruction();
> 11848:     evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_b, evex_v, eevex_x, nds_enc, pre, opc);

Suggestion:

    evex_prefix(vex_r, vex_b, vex_x, evex_r, eevex_b, evex_v, eevex_x, nds_enc, pre, opc);

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1591847091
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1591858904
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1591846721
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1591848768
PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1591848945