RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v17]

[Steve Dohrmann]

On Thu, 9 May 2024 19:32:24 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Steve Dohrmann has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   enable EEVEX encoding of vex map2 instructions when UseAVX=2 if UseAPX=true
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 4914:
> 
>> 4912:   assert(VM_Version::supports_sse4_1(), "");
>> 4913:   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
>> 4914:   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes, true);
> 
> _legacy_mode_dq and _legacy_mode_bw will be true for non AVX512DQ/BW targets, this will cause incorrectness since our scheme has been to treat those as non-legacy instructions upfront and only perform legacy demotions in leaf level routines if non of the register operand is an EGPR.

In general, the legacy mode will be set to true whenever UseAVX < 3, due to logic in the InstructionAttr ctor.

`_legacy_mode(legacy_mode || UseAVX < 3`

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1596017447