RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v17]

[Jatin Bhateja]

On Thu, 9 May 2024 21:42:34 GMT, Steve Dohrmann <duke at openjdk.org> wrote:

>> src/hotspot/cpu/x86/assembler_x86.cpp line 4914:
>> 
>>> 4912:   assert(VM_Version::supports_sse4_1(), "");
>>> 4913:   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
>>> 4914:   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes, true);
>> 
>> _legacy_mode_dq and _legacy_mode_bw will be true for non AVX512DQ/BW targets, this will cause incorrectness since our scheme has been to treat those as non-legacy instructions upfront and only perform legacy demotions in leaf level routines if non of the register operand is an EGPR.
>
> In general, the legacy mode will be set to true whenever UseAVX < 3, due to logic in the InstructionAttr ctor.
> 
> `_legacy_mode(legacy_mode || UseAVX < 3`

Hi @steveatgh ,

Still getting incorrect encoding for PINSRQ at UseAVX=0 with latest patch.

This is a legacy map3 instruction which should be promoted to Extended EVEX, encoding, there is no route in _Assembler::simd_prefix_and_encode_ which can lead to EVEX encoding at UseAVX=0.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1597065361