RFR: 8328998: Encoding support for Intel APX extended general-purpose registers [v17]

[Steve Dohrmann]

On Fri, 10 May 2024 18:11:11 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Hi @steveatgh ,
>> 
>> Still getting incorrect encoding for PINSRQ at UseAVX=0 with latest patch.
>> 
>> This is a legacy map3 instruction which should be promoted to Extended EVEX, encoding, there is no route in _Assembler::simd_prefix_and_encode_ which can lead to EVEX encoding at UseAVX=0.
>
> Similar problems with PINSRB/D/W and PEXTRB/W/D/Q

Thanks @jatin-bhateja.  I added logic to ::simd_prefix_and_encode and ::simd_prefix to conditionally allow EEVEX encoding even when UseAVX=0.  Tested with PINSR* and PEXTR*

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PR Review Comment: https://git.openjdk.org/jdk/pull/18476#discussion_r1597253753