RFR: 8332130: RISC-V: remove wrong instructions of Vector Crypto Extension

[Fei Yang]

On Tue, 14 May 2024 07:37:39 GMT, Fei Yang <fyang at openjdk.org> wrote:

>>> I think you mean the `funct3` (`OPIVV` vs `OPIVX`) encoding is wrong?
>> 
>> Yes
>
>> > I think you mean the `funct3` (`OPIVV` vs `OPIVX`) encoding is wrong?
>> 
>> Yes
> 
> From the RVV spec [1], the `funct3` encoding for `OPIVX` is 0b100, which is also reflected on the instruction encoding.
> So why would you think it's wrong? Anything I missed? 
> 
> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-arithmetic-instruction-formats

> @RealFYang the `.vx` variant expect a **scalar** register while our `vandn_vx` takes a **vector** register. If we had a use for `vandn_vx` (or any of the other removed instructions), we would need to add another section with
> 
> ```
> #define INSN(NAME, op, funct3, funct6)                                                             \
>   void NAME(VectorRegister Vd, VectorRegister Vs2, Register Rs1, VectorMask vm = unmasked) { \
>     patch_VArith(op, Vd, funct3, Rs1->raw_encoding(), Vs2, vm, funct6);                            \
>   }
> ```
> 
> But given we have no use for these instructions, I'm ok with removing them.

Ah, I see. Looks good. Thanks.

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PR Comment: https://git.openjdk.org/jdk/pull/19211#issuecomment-2109789006