RFR: 8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions [v2]

[Gui Cao]

On Sat, 11 May 2024 07:29:46 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Use iRegIorL2I to replace iRegI in AndV/OrVXorV instruct
>
> src/hotspot/cpu/riscv/riscv_v.ad line 513:
> 
>> 511: // vector-scalar and (unpredicated)
>> 512: 
>> 513: instruct vand_regI(vReg dst_src, iRegI src) %{
> 
> Do we need `iRegIorL2I` for `RegI` related instructions?

Thanks for your review. fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18999#discussion_r1601166494