Integrated: 8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions

[Gui Cao]

On Mon, 29 Apr 2024 12:17:58 GMT, Gui Cao <gcao at openjdk.org> wrote:

> Hi, We want to support vector-scalar and vector-immediate bitwise logic instructions, It was implemented by referring to RVV v1.0 [1]. please take a look and have some reviews. Thanks a lot.
> We can use the Int256VectorTests.java[2] to print the compilation log, verify and observe the generation of nodes.
> 
> For example, we can use the following command to print the compilation log of a jtreg test case:
> 
> 
> /home/zifeihan/jdk-tools/jtreg/bin/jtreg \
> -v:default \
> -concurrency:16 -timeout:50 \
> -javaoption:-XX:+UnlockExperimentalVMOptions \
> -javaoption:-XX:+UseRVV \
> -javaoption:-XX:+PrintOptoAssembly \
> -javaoption:-XX:LogFile=/home/zifeihan/jdk/Int256VectorTests_PrintOptoAssembly.log \
> -jdk:/home/zifeihan/jdk/build/linux-riscv64-server-fastdebug/jdk \
> /home/zifeihan/jdk/test/jdk/jdk/incubator/vector/Int256VectorTests.java
> 
> 
> 
>  we can observe the specified compilation log `Int256VectorTests_PrintOptoAssembly.log`, which contains the vector-scalar and vector-immediate bitwise logic node for the PR implementation.
> 
> vand_immI Node
> 
> 
> 0b4     vloadcon V3	# generate iota indices
> 0bc     vmla V2, V2, V3, V1
> 0c4     vand_immI V2, V2, #7
> 0cc     addi  R7, R30, #16	# ptr, #@addP_reg_imm
> 0d0     storeV [R7], V2	# vector (rvv)
> 
> 
> vor_regI Node
> 
> 
> 180     vor_regI V1, V1, R30
> 188     add R31, R14, R31	# ptr, #@addP_reg_reg
> 18a     addi  R31, R31, #16	# ptr, #@addP_reg_imm
> 18c     storeV [R31], V1	# vector (rvv)
> 194     addiw  R11, R11, #8	#@addI_reg_imm
> 196     blt  R11, R13, B17	#@cmpI_loop  P=0.500000 C=30564.000000
> 
> 
> vxor_regI Node
> 
> 198     vxor_regI V1, V1, R30
> 1a0     add R14, R16, R14	# ptr, #@addP_reg_reg
> 1a2     addi  R14, R14, #16	# ptr, #@addP_reg_imm
> 1a4     storeV [R14], V1	# vector (rvv)
> 1ac     addiw  R11, R11, #8	#@addI_reg_imm
> 1ae     blt  R11, R13, B21	#@cmpI_loop  P=0.500000 C=30564.000000
> 
> 
> vand_regI_masked Node
> 
> 234     B31: #	out( B40 B32 ) <- in( B30 )  Freq: 78.5481
> 234     loadV V2, [R15]	# vector (rvv)
> 23c     vand_regI_masked V2, V2, R11
> 244     storeV [R9], V2	# vector (rvv)
> 24c     mv R10, #8	# int, #@loadConI
> 24e     ble  R7, R10, B40	#@cmpI_branch  P=0.000001 C=-1.000000
> 
> 
> vor_regI_masked Node
> 
> 1ee     B32: #	out( B38 B33 ) <- in( B31 )  Freq: 75.8475
> 1ee     loadV V1, [R11]	# vector (rvv)
> 1f6     vor_regI_masked V1, V1, R31
> 1fe     addi  R11, R13, #32	# ptr, #@addP_reg_imm
> 202     bgeu  R29, R10, B38	#@cmpU_branch  P=0.000001 C=-1.000000
> 
> vxor_regI_masked Node
> 
> 1ee     B32: #	out( B38 B33 ) <- in( B31 )  Freq: 75.8475
> 1ee     loadV V1, [R11]...

This pull request has now been integrated.

Changeset: e6111517
Author:    Gui Cao <gcao at openjdk.org>
Committer: Ludovic Henry <luhenry at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/e611151796d71c40a9395cb6fbe734f36d4c1b55
Stats:     471 lines in 2 files changed: 469 ins; 0 del; 2 mod

8331281: RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions

Reviewed-by: fjiang, fyang

-------------

PR: https://git.openjdk.org/jdk/pull/18999