RFR: 8328998: Encoding support for Intel APX extended general-purpose registers

[Jatin Bhateja]

On Sat, 11 May 2024 21:21:47 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

> 
> A) With recent change register only flavors of cvtsi2ss / cvtsi2sd / cvttsd2si/ cvttss2si which are all legacy map 1 instruction and are encoded using REX prefixes at UseAVX=0 will now be promoted to EEVEX which is a fixed 4 byte prefix, we should use REX2 instead. [cvtsi2ss_MAP1_with_EEVEX.txt](https://github.com/openjdk/jdk/files/15284294/cvtsi2ss_MAP1_with_EEVEX.txt)
> 

SDE ERROR: Illegal instruction at address = 7f3aafa329a0: f3 d5 10 **0f** 2a c1
      
I debugged the cause of above assertion failure with UseAVX=0 and found two issues:-
1) Secondary map ID (0x0f) is being emitted after REX2 prefix, this should not happen since REX.M0 encodes this information.
2) REX.M0 is not being set, because we are not passing correct value for map1 argument
https://github.com/openjdk/jdk/blob/47885cbe8eb215323e9ca8f4a36d422d17521e57/src/hotspot/cpu/x86/assembler_x86.cpp#L11734

If we bring out the 0x0f to the top level assembler routines and remove following newly added codelets we can handle APX even at AVX level 0 and lift AVX512 constraint you introduced since SPECjbb2015 benchmark still [explicitly pass UseAVX=0 during measurments.](https://spec.org/jbb2015/results/res2024q1/jbb2015-20240110-01212.html#:~:text=Xms29g%20%2DXmx29g%20%2DXmn27g-,%2DXX%3AUseAVX%3D0,-%2DXX%3AParallelGCThreads%3D32)

https://github.com/openjdk/jdk/blob/47885cbe8eb215323e9ca8f4a36d422d17521e57/src/hotspot/cpu/x86/assembler_x86.cpp#L13158
https://github.com/openjdk/jdk/blob/47885cbe8eb215323e9ca8f4a36d422d17521e57/src/hotspot/cpu/x86/assembler_x86.cpp#L13187
https://github.com/openjdk/jdk/blob/47885cbe8eb215323e9ca8f4a36d422d17521e57/src/hotspot/cpu/x86/assembler_x86.cpp#L13347

I am ok to address these limitation in subsequent patches.

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PR Comment: https://git.openjdk.org/jdk/pull/18476#issuecomment-2117999627